GATED LATERAL THYRISTOR-BASED RANDOM ACCESS MEMORY (GLTRAM) CELLS WITH SEPARATE READ AND WRITE ACCESS TRANSISTORS, MEMORY DEVICES AND INTEGRATED CIRCUITS INCORPORATING THE SAME

摘要

A kind of memory device is provided, including one writes bit line, read bit line and at least one processor unit. The storage unit includes write access transistor, and read access transistor is coupled to reading bit line and the first write access transistor, and gated lateral thyristor (GLT) device is coupled to the first write access transistor. In its many features, prevent the storage unit reading interference during read operation from passing through decoupling read and write bit line.