Hybrid Josephson-CMOS Random Access Memory with Interfacing to Josephson Digital Circuits.

摘要

The work during this period brought our efforts to realize a 64-kbit hybrid Josephson-CMOS memory for 4K operation to a successful conclusion. The memory inputs and outputs are at the several-millivolt level. The inputs are first amplified to 60 mV using Suzuki stacks; these signals drive CMOS comparators, the outputs of which are at volt level, as required by the commercially manufactured 65 nm CMOS memory array. Final designs were fabricated and tested. The access time is less than 400 ps and the read power dissipation is less than 10 mW. A side project was performed to evaluate the concept for a novel wholly Josephson memory proposed by a Japanese memory expert. We found that the proposed memory cell has inadequate design margins. We realized the other goal of the project, which was to analyze the factors limiting Josephson memories. Presentations for the Applied Superconductivity Conference (ASC) in October 2012 were prepared and presented. Publications resulted. We also brought together an international group of 30 cryogenic memory researchers in a post-ASC workshop at UC Berkeley for more discussions. And presentations were made at the Superconductive Electronics Conference (ISEC) in July 2013.