On chip word line voltage with PVT tracking for memory embedded in logic process

摘要

The present disclosure is directed toward regulation of voltage for semiconductor memories. In an embodiment, a circuit for providing a controlled voltage level comprises a PMOS transistor coupled to a first voltage coupler (V_PP), the gate of the PMOS transistor being coupled to the drain of the PMOS transistor; a MOS sub-threshold current source, coupled to a second voltage coupler (ground); and a bias independent current source coupled to the MOS sub-threshold current source and the PMOS transistor intermediate the MOS sub-threshold current source and the PMOS transistor. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.