Duty cycle correction circuit and duty cycle correction method for output clock signals in the Delayed Locked Loop.

摘要

delay lock loop output clock signal with a duty cycle (duty cycle) the duty cycle correction can be corrected The duty cycle correction circuit and method are disclosed. The duty cycle correction circuit according to the present invention is provided with a reference clock signal generator and the output clock signal generator. The reference clock signal generator receives an external clock signal, in response to one of the output clock signal from among a plurality of output clock signals, and generates a reference clock signal, and correcting the duty cycle of the external clock signal. The output clock signal generator and outputs the reference clock signal delayed by a predetermined time unit each of which a plurality of the output clock signal. The duty cycle correction circuit and the duty cycle correction process according to the invention has an advantage capable of correcting the duty cycle (duty cycle) of the output clock signal of the delay locked loop by 50%.