AT-SPEED INTERCONNECT TEST CONTROLLER FOR SOC WITH HETEROGENEOUS WRAPPED CORES AND SYSTEM ON CHIP COMPRISING THE SAME

摘要

The present invention is a system-on-chip having a heterogeneous core: relates to a connecting line between the delay fault test controller checks in the core (system on chip SoC). The present invention, in the connecting line delay fault check controller to check to test the connection line delay fault between the cores in system-on-chip that includes a plurality of cores, the test clock (TCK) and said system-on-chip that is provided from the outside of the test device receives input system clock (SCK), Connection for delayed troubleshooting, testing upon generating the test clock and the system clock, the combination of connectors delay troubleshooting, testing and clock (Real_Clock) output and said in testing other than checking test Connection delay fault a clock generating unit that outputs the test clock; Tap control unit for generating a plurality of signals and the delayed signal Late_Update_DR a plurality of signals of the signal as much as 1.5 Update_DR test clock according to the IEEE 1149.1 standard receives the connection line delay for fault checking test clock or the test clock from said clock generating unit; And receive input for the Update_DR signal and Late_Update_DR signal, connecting line delay outputs a failure check the Late_Update_DR signal during the test and connection line delay testing when Connection Delay Fault Check test controller including a signal selector for outputting the Update_DR signal other than the failure check test to provide. In the above on-the invention the system includes an interface control unit for changing into a signal suitable for connecting line delayed signal of the failure check test according to the P1500 core chip, it is possible to check connection line delay fault between heterogeneous cores test covered with IEEE 1149.1 and P1500. ; IEEE 1149.1, P1500, connectors, delay, failure, tab controls, applied (Update), Capture (Capture)