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AT-SPEED INTERCONNECT TEST CONTROLLER FOR SYSTEM ON CHIP USING MULTIPLE SYSTEM CLOCK AND HAVING HETEROGENEOUS CORES
AT-SPEED INTERCONNECT TEST CONTROLLER FOR SYSTEM ON CHIP USING MULTIPLE SYSTEM CLOCK AND HAVING HETEROGENEOUS CORES
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机译:使用多个系统时钟并具有异类芯的芯片上系统的高速互连测试控制器
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摘要
The present invention relates to a connecting line delay fault test controller capable of performing the delay fault test connection line between heterogeneous cores in system-on-chip. The present invention, tap control unit for outputting a plurality of signals for inter-core connecting line test according to the IEEE 1149.1 Standard; Connection delay when the failure test is started from the time that output 1 from the time that Capture_DR state starts to falling edge of the test clock in its follow-up state, and when the rest, the first enable signal and Update_DR state to output a 0 starting Capture_DR 1 to the point where the output state is terminated, and if the rest of the enable signal generating unit which generates the second enable signal to output a 0; Receive input the system clock and the first enable signal, while outputting 0 in the initial state outputs a 1 in the first rising edge of the system clock after the first enable signal is output to 1, and wherein the first enable If the signal is 0, the output unit generates a first control signal for generating a signal Late_Update_DR back to the initial state; Receive input the system clock and the first enable signal, while outputs a 1 in the initial state outputs a 0 on the first rising edge of the system clock after the first enable signal is output 1 and, at the next rising edge including a generating a second control signal for generating a sck_DR signal for outputting a first, connecting line delay when the malfunction test is run, that in the Capture_DR state of the tap controller, the rising edge and the capture of the Late_Update_DR signal that the update has occurred occurred It provides a connection line delay fault test controller, characterized in that that occur within a system clock to the rise of the land sck_DR signal. ; IEEE 1149.1, P1500, connectors, delay, failure, tab controls, updating, capture, multi-system clock
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