首页> 外国专利> AT-SPEED INTERCONNECT TEST CONTROLLER FOR SYSTEM ON CHIP USING MULTIPLE SYSTEM CLOCK AND HAVING HETEROGENEOUS CORES

AT-SPEED INTERCONNECT TEST CONTROLLER FOR SYSTEM ON CHIP USING MULTIPLE SYSTEM CLOCK AND HAVING HETEROGENEOUS CORES

机译:使用多个系统时钟并具有异类芯的芯片上系统的高速互连测试控制器

摘要

The present invention relates to a connecting line delay fault test controller capable of performing the delay fault test connection line between heterogeneous cores in system-on-chip. The present invention, tap control unit for outputting a plurality of signals for inter-core connecting line test according to the IEEE 1149.1 Standard; Connection delay when the failure test is started from the time that output 1 from the time that Capture_DR state starts to falling edge of the test clock in its follow-up state, and when the rest, the first enable signal and Update_DR state to output a 0 starting Capture_DR 1 to the point where the output state is terminated, and if the rest of the enable signal generating unit which generates the second enable signal to output a 0; Receive input the system clock and the first enable signal, while outputting 0 in the initial state outputs a 1 in the first rising edge of the system clock after the first enable signal is output to 1, and wherein the first enable If the signal is 0, the output unit generates a first control signal for generating a signal Late_Update_DR back to the initial state; Receive input the system clock and the first enable signal, while outputs a 1 in the initial state outputs a 0 on the first rising edge of the system clock after the first enable signal is output 1 and, at the next rising edge including a generating a second control signal for generating a sck_DR signal for outputting a first, connecting line delay when the malfunction test is run, that in the Capture_DR state of the tap controller, the rising edge and the capture of the Late_Update_DR signal that the update has occurred occurred It provides a connection line delay fault test controller, characterized in that that occur within a system clock to the rise of the land sck_DR signal. ; IEEE 1149.1, P1500, connectors, delay, failure, tab controls, updating, capture, multi-system clock
机译:连接线延迟故障测试控制器技术领域本发明涉及一种能够在片上系统中的异构核之间执行延迟故障测试连接线的连接线延迟故障测试控制器。本发明的抽头控制单元,用于输出多个信号,用于根据IEEE 1149.1标准的芯间连接线测试;从Capture_DR状态开始的时间开始到输出1的时间开始故障测试,直到处于后续状态的测试时钟的下降沿为止的连接延迟,其余时间则为第一个使能信号和Update_DR状态输出的连接延迟0从Capture_DR 1开始直到输出状态终止,如果其余的使能信号产生单元产生第二使能信号则输出0;接收输入的系统时钟和第一使能信号,同时在初始状态下输出0时,在将第一使能信号输出为1之后,在系统时钟的第一上升沿输出1。 ,输出单元产生第一控制信号,以产生信号Late_Update_DR回到初始状态。接收输入的系统时钟和第一使能信号,而在初始状态下输出1则在输出第一使能信号1之后在系统时钟的第一个上升沿输出0,在下一状态包括产生一个第二控制信号,用于在运行故障测试时生成sck_DR信号,以输出第一连接线路延迟,在抽头控制器的Capture_DR状态下,发生上升沿并捕获发生更新的Late_Update_DR信号。提供了一种连接线延迟故障测试控制器,其特征在于发生在系统时钟内到焊盘sck_DR信号的上升。 ; IEEE 1149.1,P1500,连接器,延迟,故障,选项卡控件,更新,捕获,多系统时钟

著录项

  • 公开/公告号KR100694315B1

    专利类型

  • 公开/公告日2007-03-14

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20050016797

  • 发明设计人 박성주;장연실;

    申请日2005-02-28

  • 分类号G01R31/28;

  • 国家 KR

  • 入库时间 2022-08-21 20:32:41

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