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Digital control circuit and method for clock signal production in integrated circuits has phase detector, control circuit filter and two phase generators

机译:用于集成电路中时钟信号产生的数字控制电路和方法,具有鉴相器,控制电路滤波器和两相发生器

摘要

A digital control circuit for clock signal production comprises at least one phase detector (PD,DL,P11,SDL,P12) with reference signal input (12) and feedback input (14), at least one control circuit filter (DLF) with corrector signal input (16) and control output (18,24) and two phase generators with clock-separated outputs (22,28). An independent claim is also included for a method for clock signal production comprising the above.
机译:用于产生时钟信号的数字控制电路包括至少一个具有参考信号输入(12)和反馈输入(14)的鉴相器(PD,DL,P11,SDL,P12),至少一个具有校正器的控制电路滤波器(DLF)信号输入(16)和控制输出(18,24)以及两个带有时钟分离输出(22,28)的相位发生器。包括以上内容的用于时钟信号产生的方法也包括独立权利要求。

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