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Metal oxide semiconductor transistor manufacture for random access static memory, by forming vias contacting a gate and source and drain regions on other side of channel region with respect to the gate

机译:用于金属氧化物半导体晶体管制造,用于随机存取静态存储器,方法是在通道区域的相对于栅极的另一侧形成与栅极以及源极和漏极区域接触的过孔

摘要

A metal oxide semiconductor (MOS) transistor is manufactured by forming vias (50, 51, 52) contacting a gate and source and drain regions (39, 41) on other side of a channel region (30) with respect to the gate. The semiconductor layer is made of silicon and has a thickness of 5-15 nm, the dopant for forming the amorphous regions being germanium implanted at a dose of 1 x10 15at/cm 2at 3-8 keV. Manufacture of a MOS transistor comprises forming an insulated gate on a portion of a semiconductor layer of a first conductivity type delimited by a periphery, forming amorphous regions on either side of a central region of the layer underlying the gate, turning over the entire structure, totally etching the amorphous regions, where recesses are formed between the central region and the periphery, and depositing in the recesses only a conductive material capable of forming the source and drain regions of the transistor, where vias contacting the gate and the source and drain regions of the transistor are formed on the other side of a channel region with respect to the gate. The semiconductor layer is made of silicon and has a thickness of 5-15 nm, the dopant for forming the amorphous regions being germanium implanted at a dose of 1 x10 15at/cm 2at 3-8 keV.
机译:通过形成通孔(50、51、52)来形成金属氧化物半导体(MOS)晶体管,该通孔(50、51、52)相对于栅极在沟道区域(30)的另一侧上与栅极以及源极和漏极区域(39、41)接触。半导体层由硅制成并且具有5-15nm的厚度,用于形成非晶区的掺杂剂以3×8keV以1×10 1> 5> at / cm 2> 1的剂量注入锗。 MOS晶体管的制造包括:在第一导电类型的半导体层的一部分上,该绝缘层的一部分形成绝缘栅,该半导体层由外围界定;在栅下面的层的中央区域的任一侧上形成非晶区,翻转整个结构,完全蚀刻非晶区,在该非晶区的中心区域和外围之间形成凹槽,并且仅在该凹槽中沉积能够形成晶体管的源极和漏极区域的导电材料,其中通孔接触栅极以及源极和漏极区域相对于栅极,在沟道区的另一侧上形成晶体管的栅极。半导体层由硅制成并且具有5-15nm的厚度,用于形成非晶区的掺杂剂以3×8keV以1×10 1> 5> at / cm 2> 1的剂量注入锗。

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