Pulse extraction system which stores ADC samples into two partitioned memory buffers and switches buffers upon detecting a pulse trailing edge

摘要

Digital samples corresponding to a pulsed input signal are provided at one output of an ADC (2) from where they are presented to an external memory (4) for storage and a second output of the ADC (2) from where they are supplied to a pulse extraction circuit (5). The pulse extraction circuit (5) includes a trigger circuit (6) that provides triggers whenever the (digitised) input signal crosses one or more trigger levels in order to detect the leading and trailing edges of pulses in the input signal. The positive (leading edge) and negative (trailing edge) trigger signals are passed to a pulse capture circuit (7) which provides a RAM Write enable signal to the external memory (4) to enable the digital samples from the ADC (2) to be stored at given addresses in a given memory buffer (14) of the external memory (4). The memory is divided into a number of buffers, each with loop back, and the digital samples are stored in both a Current memory buffer and a Next memory buffer. When a negative trigger signal is provided, the Current buffer stops storing further samples, the Next buffer becomes the Current buffer and a new buffer becomes the Next buffer. Each buffer thereby stores an extracted pulse and by storing the digital samples in two buffers, the Current buffer and the Next buffer, no data is lost during the transition between one pulse and the next.