METHOD AND PROGRAM FOR DESIGNING MASK LAYOUT FOR INTEGRATED CIRCUIT AND OPTIMIZATION METHOD OF MASK LAYOUT OF INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a method for correcting an optical proximity effect on a mask layout of an integrated circuit.;SOLUTION: The method ensures an appropriate functional interaction among circuit features by including functional interlayer and intra-layer constraints on a wafer. The functional constraints used by the present invention are applied to simulated wafer images, which reduces or eliminates EPE (edge placement error) constraints with respect to positions of wafer images while ensuring an appropriate functional interaction.;COPYRIGHT: (C)2008,JPO&INPIT