CIRCUIT ANALYSIS METHOD, CIRCUIT ANALYSIS PROGRAM, AND CIRCUIT SIMULATION DEVICE
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机译:电路分析方法,电路分析程序及电路仿真装置
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摘要
PROBLEM TO BE SOLVED: To reduce the circuit area of a semiconductor device to be designed.;SOLUTION: A circuit simulation device 10 includes: a delay time verifying part 252 for calculating a delay time Td under a prescribed environmental condition concerning static timing verification with respect to a logical circuit 100 after layout, and performing hold verification; and a layout correcting part 253. When hold violation is determined in the hold verification, the delay time verifying part 252 selects a correcting method corresponding to the environmental condition from the plurality of layout correcting methods. The layout correcting part 253 corrects the layout of the logical circuit with the use of the correcting method selected by the delay time verifying part.;COPYRIGHT: (C)2008,JPO&INPIT
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机译:解决的问题:为了减小要设计的半导体器件的电路面积;解决方案:电路仿真设备10包括:延迟时间验证部分252,用于在a下计算延迟时间T d Sub>。在布局之后对逻辑电路100规定与静态时序验证有关的环境条件,并进行保持验证;当在保持验证中确定保持违反时,延迟时间验证部分252从多种布局校正方法中选择与环境条件相对应的校正方法。布局校正部分253使用由延迟时间验证部分选择的校正方法来校正逻辑电路的布局。;版权:(C)2008,JPO&INPIT
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