首页> 外国专利> MULTI-CHIP LAMINATION SUBSTRATE, MULTI-CHIP LAMINATION MOUNTING STRUCTURE USING THE SAME, AND APPLICATION OF THE SAME

MULTI-CHIP LAMINATION SUBSTRATE, MULTI-CHIP LAMINATION MOUNTING STRUCTURE USING THE SAME, AND APPLICATION OF THE SAME

机译:多芯片层叠基板,使用该芯片的多芯片层叠结构及其应用

摘要

PPROBLEM TO BE SOLVED: To provide a multi-chip lamination substrate, a multi-chip lamination mounting structure using the same, and an application of the same in which each chip group can independently operate. PSOLUTION: A multi-chip lamination substrate 200 at least has a first wire bonding finger 211, a second wire bonding finger 212, a trace, and a loop wiring. The first wire bonding finger 211 and the second wire bonding finger 212 are adjacent to a die attaching area. The loop wiring is connected in series to the first wire bonding finger 211 and the second wire bonding finger 212, and also connected to the trace. A multi-chip lamination mounting structure includes the substrate 200, a first chip 50 provided in the die attaching area, and a second chip 60 laminated on the first chip 50. PCOPYRIGHT: (C)2009,JPO&INPIT
机译:

要解决的问题:提供多芯片层叠基板,使用该多芯片层叠基板的多芯片层叠安装结构以及每个芯片组可以独立操作的相同应用。

解决方案:多芯片层压基板200至少具有第一引线键合指211,第二引线键合指212,迹线和环形布线。第一引线键合指211和第二引线键合指212与管芯附接区域相邻。环形布线串联连接至第一引线键合指211和第二引线键合指212,并且还连接至迹线。多芯片层叠安装结构包括基板200,设置在管芯附着区域中的第一芯片50和层压在第一芯片50上的第二芯片60。

COPYRIGHT:(C)2009,JPO&INPIT

著录项

  • 公开/公告号JP2008258521A

    专利类型

  • 公开/公告日2008-10-23

    原文格式PDF

  • 申请/专利权人 POWERTECH TECHNOLOGY INC;

    申请/专利号JP20070101475

  • 发明设计人 WU CHIH-WEI;HSU HUNG-HSIN;

    申请日2007-04-09

  • 分类号H01L25/065;H01L25/07;H01L25/18;

  • 国家 JP

  • 入库时间 2022-08-21 20:24:13

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