Is scalable for system-on-chip network processor unit multi-threaded, multi-processing, in high-performance, interconnection scheme for large-scale

摘要

Is scalable for system-on-chip network processor unit multi-threaded, multi-processing, it is an interconnection scheme highly functional. More than one master, which is formed in the cluster of several, multiple targets, and an apparatus for implementing the present technique is controlled to include a chassis interconnect, and selectively connected to a given target master predetermined . In one embodiment, a set of bus which consists of a set of a plurality of bus lines connected between the several targets and several clusters forming a crossbar interconnect, corresponding to the instruction bus, the chassis interconnect is written to the target pull data bus, and includes a push data bus for target reads for writing. The multiplexer circuit for each of the push data bus, is used to connect selectively to a given target to a given cluster, the data and instructions and a given cluster command bus, pull data bus, and to enable it from being passed between a given target.