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And a method for scaling selectively integrated circuit design system, the program (selective scaling of integrated circuits)

机译:一种用于选择性缩放集成电路设计系统的方法,程序(集成电路的选择性缩放)

摘要

The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.
机译:本发明包括一种用于通过以下方式选择性地缩放集成电路(IC)设计的解决方案:层,区域或单元,或这些的组合。选择性缩放技术可以在设计生命周期内与具有过程和成品率反馈的制造系统一起应用在反馈回路中,以保留层次结构的方式提高早期过程中的良率。本发明消除了使设计师参与提高产量的需要。

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