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STRAINED SPACER DESIGN FOR PROTECTING HIGH-K GATE DIELECTRIC
STRAINED SPACER DESIGN FOR PROTECTING HIGH-K GATE DIELECTRIC
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机译:保护高K栅极介电层的应变间隔设计
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摘要
A semiconductor device pair is provided. The semiconductor device pair comprises a semiconductor substrate comprising a first gate structure with a first type polarity and a second gate structure with a second type polarity, the first and the second gate structures comprise a high-K gate dielectric. A plurality of oxygen-free offset spacer portions are adjacent either side of the respective first and second gate structures, each comprising a stressed dielectric layer, to induce a desired strain on a respective channel region while sealing respective high-K gate dielectric sidewall portions, wherein the oxygen-free offset spacer portions adjacent either side of the first gate structure and the oxygen-free offset spacer portions adjacent either side of the second gate structure are formed with different shapes.
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