Reconfigurable programmable logic device with P-channel non-volatile memory cells

摘要

A system is disclosed for constructing a reconfigurable programmable logic device (PLD) comprising a first P-channel nonvolatile memory cell with a first source, a first drain and a first gate coupled to a first input node, a second P-channel nonvolatile memory cell with a second source, a second drain and a second gate coupled to a second input node, and an NMOS transistor with a third source and a third drain, wherein the first and second sources are commonly connected to a positive voltage supply (Vcc), the first, second and third drains are commonly connected to an output node and the third source is coupled to a complementary low voltage supply (Vss).