首页> 外国专利> SYSTEM AND METHOD FOR CHECKING A LENGTH OF A WIRE PATH BETWEEN A CAPACITOR AND A VIA OF A PCB DESIGN

SYSTEM AND METHOD FOR CHECKING A LENGTH OF A WIRE PATH BETWEEN A CAPACITOR AND A VIA OF A PCB DESIGN

机译:用于确定电容器和PCB设计之间的走线长度的系统和方法

摘要

A method for checking a length of a wire path between a capacitor and a via of the PCB design is disclosed. The method includes: obtaining length criteria and information on capacitors from a database; selecting one or more capacitors and pins of selected capacitors from the obtained information on capacitors, and selecting one of the length criteria; obtaining positions of selected capacitors, and positions of vias corresponding to the positions of selected capacitors from the database; calculating each length of a wire path between a selected capacitor and a corresponding via according to the position of the capacitor and the position of the via; determining whether each calculated length of a wire path between a selected capacitor and a corresponding via is acceptable according to a comparison with the selected length criterion; and outputting check results of the determining step. A related system is also disclosed.
机译:公开了一种用于检查PCB设计的电容器和通孔之间的布线路径的长度的方法。该方法包括:从数据库获得长度标准和关于电容器的信息;以及从所获得的电容器信息中选择一个或多个电容器和所选电容器的引脚,并选择长度准则之一;从数据库中获取所选电容器的位置以及与所选电容器的位置相对应的过孔的位置;根据电容器的位置和通孔的位置,计算选定的电容器与对应的通孔之间的布线路径的每个长度;根据与所选择的长度准则的比较,确定所选择的电容器与对应的通孔之间的布线路径的每个计算出的长度是否可接受;输出判断步骤的检查结果。还公开了相关的系统。

著录项

  • 公开/公告号US2008189669A1

    专利类型

  • 公开/公告日2008-08-07

    原文格式PDF

  • 申请/专利权人 SHOU-KUO HSU;CHUN-SHAN HSIAO;

    申请/专利号US20070951284

  • 发明设计人 SHOU-KUO HSU;CHUN-SHAN HSIAO;

    申请日2007-12-05

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 20:11:42

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