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Digital correction of nonlinearity errors of multibit delta-sigma digital to analog converters

机译:多位delta-sigma数模转换器非线性误差的数字校正

摘要

Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.
机译:提供了针对误差反馈DAC的多位ADAC非线性的数字校正。低分辨率校准ADC(CADC)估算(在线或离线)多位ADAC的积分非线性(INL)误差,并将其存储在随机存取存储器(RAM)表中。然后使用INL值补偿数字域中ADAC的失真。当此补偿与不匹配成形技术(例如DWA)结合使用时,CADC的分辨率要求可以大大放宽。所提出的用于误差反馈调制器的校正电路的实施本质上很简单,因为校正仅需要数字求和,而无需任何额外的数字滤波。

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