Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques

摘要

New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs:A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates;B) In core pair-wise frequency Dependent RL extraction;C) In core equivalent circuit synthesis;D) caching and partitioning RL extraction techniques for run time efficiency; andE) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R₁₂.