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Logic circuit, system for reducing a clock skew, and method for reducing a clock skew
Logic circuit, system for reducing a clock skew, and method for reducing a clock skew
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机译:逻辑电路,减少时钟偏斜的系统以及减少时钟偏斜的方法
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摘要
A logic circuit includes a first flip-flop configured to include a first input terminal introducing a clock, a first output terminal supplying the clock and a first internal wiring connecting the first input terminal and the first output terminal, and a second flip-flop configured to be adjacent to the first flip-flop and be supplied with the clock from the first output terminal.
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