Image-rejection mixers having high linearity and high gain and RF circuits using the same

摘要

An integrated semiconductor image-rejection mixer having high linearity and high gain. In addition to the components of a classic image-rejection architecture, the present mixer has a high-frequency current-diverting stage that permits the operation of the output stage with high conversion gain and sufficient headroom for good linearity, even in cases where the supply voltage is relatively low (such as 3 V). The conversion gain of the mixer and its image-rejection performance can be changed by changing the load resistances and the elements of the output polyphase network, with minor effects on linearity and no change in power consumption or DC levels. The power consumption of the image-rejection mixer is low because no additional DC current is required for buffers or amplifier stages. A direct upconversion double quadrature mixer stacked with an RF VGA and load tank using an R-C, R-6C single pole current mode signal path I/Q combiner and employing a common stage as both the IQ combiner termination and the VGA control point is also disclosed.