首页> 外国专利> INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR DETERMINING THE PARASITIC NON-REACTIVE RESISTANCE OF AT LEAST THE LEAD OF AT LEAST ONE MEMORY CELL OF AN INTEGRATED CIRCUIT ARRANGEMENT

INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR DETERMINING THE PARASITIC NON-REACTIVE RESISTANCE OF AT LEAST THE LEAD OF AT LEAST ONE MEMORY CELL OF AN INTEGRATED CIRCUIT ARRANGEMENT

机译:集成电路布置和用于确定集成电路布置的至少一个存储单元中的至少一个的寄生非电抗的方法

摘要

An integrated circuit arrangement (300) has at least one electronic component (302), and also at least one resistance determining circuit that is coupled to the electronic component and is monolithically integrated with the latter and serves for determining the parasitic non-reactive resistance (303) of at least the lead to the at least one electronic component.
机译:集成电路装置(300)具有至少一个电子组件(302),以及至少一个电阻确定电路,该电阻确定电路耦合到该电子组件并与该电子组件单片集成,并用于确定寄生非电抗电阻(至少303的引线)。

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