The invention relates to microelectronics, in particular to producing integrated circuits (IC) using complementary bipolar transistors NPN and PNP provided with carriers of different conductivity types. The processing speed of integrated circuits is obtainable by using complementary transistors, the minimum size of the emitter areas of which, determining processing speed, is less than the minimum size in a lithography, due to the fact that the actual size of the emitter areas of both types of transistors is determined by the size of etching of an oxide silicon thin layer under the electrode of an emitter at an indefinitely small calculated value of submicron or ultra submicron size, which is subsequently fillable with polycrystal silicon.
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