An intelligent data bus interface (30) using a triple-port memory (32) having three independent data ports (32a, 32b, 32c) that provide simultaneous access to the data stored in the memory (36) to two bi-directional data buses (46, 50) and to a data processor (34). The two data buses (46, 50) and the processor (34) are coupled to separate data ports and each is able to independently access data in the triple-port memory (32) at full data rate of each. Because of the use of the triple-port memory (32) no data copying or moving is required in order to provide access to the data to the processor (34) or the data buses (46, 50). The intelligent data bus interface (30) is particularly suitable for handling encryption/decryption, network protocol and PCI/SCI bridging at full speed at any of its ports without burdening a host processor.
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