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FREQUENCY-MULTIPLYING DELAY LOCKED LOOP AND METHOD FOR GENERATING AN OUTPUT CLOCK SIGNAL USING ITS
FREQUENCY-MULTIPLYING DELAY LOCKED LOOP AND METHOD FOR GENERATING AN OUTPUT CLOCK SIGNAL USING ITS
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机译:倍频延迟锁定环和使用其生成输出时钟信号的方法
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摘要
A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.
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