Multigate i.e. dual gate, fin-FET manufacturing method for computing equipment, involves forming wall i.e. spacer, that delimits cavity, in matrix layer, where wall has structural properties that are different from rest of matrix layer

摘要

The method involves forming a channel (20) of a dual-gate fin-FET on a massive/multi-layer substrate (10) i.e. semiconductor-on-insulator structure, and forming a gate dielectric layer on channel`s outer surfaces. An electrosensitive/photosensitive matrix layer (30) is formed on the substrate. A gate of the transistor is formed in a cavity (34). A source and a drain of the transistor are formed at ends of the channel situated outside the cavity. A wall (31) i.e. spacer, that delimits the cavity, is formed in the layer (30), and has structural properties different from rest of the layer (30). The matrix layer is made of flowable oxide(RTM: hydrogen silsesquioxane). The channel has blades (21) that are provided with a stacking of silicon and silicon-germanium layers. An independent claim is also included for a field effect transistor comprising a spacer.