首页> 外国专利> Method for manufacturing integrated circuit, involves performing partial etching on layer through another layer until cavity crosses through layer, engraving partial layers in side walls of cavity, and completely removing former layer

Method for manufacturing integrated circuit, involves performing partial etching on layer through another layer until cavity crosses through layer, engraving partial layers in side walls of cavity, and completely removing former layer

机译:用于制造集成电路的方法包括:在穿过另一层的层上进行部分蚀刻,直到腔体穿过该层为止;在腔体的侧壁中雕刻部分层;以及完全去除先前的层。

摘要

The method involves forming a through cavity (1) in a layer, and performing a partial etching on another layer (DE) to deepen depression in the latter layer, where the layers form a step (3). A partial isotropic etching of the former layer is performed using peroxide to broaden edges of the cavity filled with metal. Another partial etching of the latter layer is performed through the former layer until the cavity crosses through the latter layer. The partial layers are engraved in side walls of the cavity. The former layer is completely removed. An independent claim is also included for an integrated circuit.
机译:该方法包括在层中形成通孔(1),并且在另一层(DE)上执行部分蚀刻以加深后一层中的凹陷,其中各层形成步骤(3)。使用过氧化物对前一层进行部分各向同性蚀刻,以加宽填充有金属的空腔的边缘。后一层的另一部分蚀刻穿过前一层进行,直到腔体穿过后一层为止。局部层刻在空腔的侧壁上。前一层被完全去除。对于集成电路也包括独立权利要求。

著录项

  • 公开/公告号FR2975826A1

    专利类型

  • 公开/公告日2012-11-30

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS (CROLLES 2) SAS;

    申请/专利号FR20110054637

  • 发明设计人 VANNIER PATRICK;

    申请日2011-05-27

  • 分类号H01L21/308;H01L23/48;

  • 国家 FR

  • 入库时间 2022-08-21 16:21:12

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