JITTER REDUCTION CIRCUIT FOR REDUCING JITTER OF CLOCK GENERATOR

摘要

PROBLEM TO BE SOLVED: To provide a jitter reduction circuit for reducing jitter by suppressing a component of 1/2 carrier frequency and a frequency component that is an odd-number multiple thereof, in particular, in a phase noise component that generates jitter.;SOLUTION: The jitter reduction circuit for reducing jitter of a clock generator includes a power distributor 10, a delay unit 20 and a power synthesizer 30. The power distributor distributes an output of an oscillator 1 into four outputs, for example. The distributor outputs are input to a delay circuit 200 of the delay unit 20, respectively. The delay unit 20 does not attenuate a carrier frequency component and a high-order higher harmonic wave component thereof but delays a component of 1/2 carrier frequency and a component of odd-number multiple thereof so as to suppress them, respectively. These outputs are then synthesized by the power synthesizer 30 and output as a jitter-reduced clock signal.;COPYRIGHT: (C)2009,JPO&INPIT