Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices

摘要

A clock driver circuit includes a phase-lock loop that generates a processed clock signal from an input clock signal. The processed clock signal is applied to a series of delay elements each of which has an output coupled to the input of a respective driver circuit. The outputs of the driver circuits are coupled to respective clocked circuits through respective conductors. The length of each conductor may vary from the lengths of other conductors. The longer conductors are coupled to upstream delay elements and the shorter conductors are coupled to downsteam delay elements so that the clock signals are applied to respective clocked circuits at substantially the same time. The delay elements thus compensate for variations in the propagation time of the clock signals as they are coupled to the clocked circuits.