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Device and Method for Limiting Di/Dt Caused by a Switching FET of an Inductive Switching Circuit

机译:限制由感应开关电路的开关FET引起的Di / Dt的装置和方法

摘要

A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes:An auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt.An auxiliary FET in parallel with the main switching FET. The auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a pre-determined maximum rate of decrease, the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt.;The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain. The auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.
机译:提出了一种用于限制在主开关FET关断期间由电感开关电路引起的di / dt的电路。限制di / dt的电路包括: 与主开关FET串联的辅助电感器,用于感应与di / dt成比例的辅助感应电压。 与主开关FET并联的辅助FET。连接辅助FET栅极以产生等于辅助感应电压的栅极电压。当di / dt趋于超过预定的最大下降率时,辅助FET产生一个辅助电流分量,抵消了di / dt的进一步减小。 ; FET可以由具有共享源极和漏极的单个芯片形成。辅助电感器可以实现为将主开关FET连接至其设备端子的固有要求的键合线的寄生电感,从而简化了封装并降低了成本。

著录项

  • 公开/公告号US2009243715A1

    专利类型

  • 公开/公告日2009-10-01

    原文格式PDF

  • 申请/专利权人 SANJAY HAVANUR;

    申请/专利号US20090479552

  • 发明设计人 SANJAY HAVANUR;

    申请日2009-06-05

  • 分类号H03H11/00;

  • 国家 US

  • 入库时间 2022-08-21 19:35:33

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