BUILT-IN REDUNDANCY ANALYZER AND METHOD FOR REDUNDANCY ANALYSIS

摘要

A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault (“fault memory” for short) is identified and a parameter is provided according to the identification code. The parameter includes the length of row address, the length of column address, the length of word, the number of redundancy rows, and the number of redundancy columns of the fault memory. Since the parameter of every individual repairable memory is different, the fault location is converted into a general format according to the parameter for easier processing. A redundancy analysis is then performed according to the parameter and the converted fault location, and the analysis result is converted from the general format to the format of the fault memory and output to the fault memory.