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Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization
Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization
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机译:用于时钟偏斜调度和优化的VLSI同步电路的设计方法
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摘要
A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.
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