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Large Scale Clock Skew Scheduling Techniques For Improved Reliability Of Digital Synchronous VLSI Circuits

机译：大规模时钟偏移调度技术可提高数字同步VLSI电路的可靠性

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Roy Mader; Eby G. Friedman; Ami Litman; Ivan S. Kourtev;
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年度 2002
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1. An introduction to standard-cell VLSI design: Very large scale integration (VLSI) is becoming an important means of producing electronic circuits at low cost, on tight schedules, and with protection for proprietary designs [J] . Kessler A.J., Ganesan A. Potentials, IEEE . 1985,第3期

机译：标准单元VLSI设计简介：超大规模集成（VLSI）成为重要的低成本生产电子电路的方法，时间表紧迫，并具有专有设计的保护
2. SCKVdd: A Scalable Clock-Controlled Self-Stabilized Voltage Technique for Low Power CMOS Digital Circuits [J] . Cheng Ching-Hwa ACM Journal on Emerging Technologies in Computing Systems . 2016,第1期

机译：SCKVdd：适用于低功率CMOS数字电路的可扩展时钟控制自稳定电压技术
3. Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches [J] . Hyein Lee, Seungwhun Paik, Youngsoo Shin Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2010,第3期

机译：脉冲宽度分配和时钟偏斜调度：基于脉冲锁存器优化时序电路
4. Large scale clock skew scheduling techniques for improved reliability of digital synchronous vlsi circuits [C] . Mader, R., Friedman, . 2002

机译：大规模时钟偏斜调度技术可提高数字同步VLSI电路的可靠性
5. Techniques for Enhancing Reliability in VLSI Circuits [D] . Hyman, Ransford, Jr. 2011

机译：用于提高VLSI电路可靠性的技术
6. Reaction Systems and Synchronous Digital Circuits [O] . Zeyi Shang, Sergey Verlan, Ion Petre, 2019

机译：反应系统和同步数字电路
7. Clock Skew Scheduling for Improved Reliability via Quadratic Programming [O] . Ivan S. Kourtev, Eby G. Friedman 1999

机译：时钟偏斜调度，通过二次编程提高可靠性

Large Scale Clock Skew Scheduling Techniques For Improved Reliability Of Digital Synchronous VLSI Circuits

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