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Setting fail bit verification circuit with different reference fail numbers and a non-volatile semiconductor memory device including the same
Setting fail bit verification circuit with different reference fail numbers and a non-volatile semiconductor memory device including the same
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机译:设置具有不同参考故障号的故障位验证电路以及包括该故障位验证电路的非易失性半导体存储器件
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摘要
A reference fail bit verification circuit includes a fail bit counter which counts a number of fail bits to generate a first counting signal and a second counting signal, the first counting signal and the second counting signal being activated in response to the number of fail bits counted. The circuit also includes a bit verification block which generates a reference bit verification signal that is activated in response to a transition of the first counting signal and the second counting signal, wherein the reference bit verification signal is activated in response to at least one of the activation of the first counting signal in a first mode, and the activation of the second counting signal in a second mode.
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