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A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

机译:用于非易失性电路设计的混合磁性/互补金属氧化物半导体三上下文存储位单元

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摘要

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.
机译:经过数十年的不断扩展以适应摩尔定律,现在看来常规​​的基于硅的器件正在接近其物理极限。在当今的深亚微米节点中,出现了许多影响制造过程以及片上微电子系统功能的短通道效应和量子效应。除了基本的电子电荷以外,利用电子的固有自旋及其相关的磁矩的自旋电子器件是有希望解决这些规模威胁的解决方案。与CMOS技术兼容,此类器件具有抗辐射,无限耐久性,非挥发性,密度增加等方面的良好协同作用。在本文中,我们提出了一种能够存储和处理的混合(磁性/ CMOS)电池电气和磁性数据。该单元基于垂直自旋传递扭矩磁性隧道结(STT-MTJ),适用于磁性随机存取存储器和可重新编程的计算(非易失性寄存器,处理器高速缓存存储器,磁场可编程门阵列等) 。为了展示混合电池的潜力,我们物理上实现了一个小型混合存储模块,其中磁性部分使用45 nm×45 nm圆形MTJ,而CMOS部分使用28 nm完全耗尽绝缘体上硅(FD-SOI)技术。我们还报告了电池在面积,鲁棒性,读/写速度和能耗方面的性能测量。

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  • 来源
    《Journal of Applied Physics》 |2014年第13期|134316.1-134316.9|共9页
  • 作者单位

    LIRMM-University of Montnellier 2/UMR CNRS 5506,161 Rue Ada, 34095 Montpellier, France;

    LIRMM-University of Montnellier 2/UMR CNRS 5506,161 Rue Ada, 34095 Montpellier, France;

    LIRMM-University of Montnellier 2/UMR CNRS 5506,161 Rue Ada, 34095 Montpellier, France;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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