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Methods of forming integrated circuit devices having gate electrodes formed on non-uniformly thick gate insulating layers

机译:形成具有在非均匀厚的栅极绝缘层上形成的栅电极的集成电路器件的方法

摘要

Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.
机译:形成集成电路器件的方法包括在半导体衬底内的并排位置处形成第一器件隔离区和第二器件隔离区,从而在其间限定半导体有源区。这些第一和第二器件隔离区具有相对于半导体有源区垂直延伸的侧壁。在半导体有源区的表面上形成第一栅绝缘层。与半导体有源区相对延伸的第一栅极绝缘层的中央部分被减薄,从而限定了在第一器件隔离区和第二器件隔离区的侧壁附近延伸的栅极绝缘残留物。在栅极绝缘残渣上形成第二栅极绝缘层,从而产生厚度不均匀的第三栅极绝缘层。在非均匀厚度的第三栅绝缘层上形成栅电极。

著录项

  • 公开/公告号US7541243B2

    专利类型

  • 公开/公告日2009-06-02

    原文格式PDF

  • 申请/专利权人 DONG-SEOG EUN;SUNG-NAM CHANG;

    申请/专利号US20070670546

  • 发明设计人 DONG-SEOG EUN;SUNG-NAM CHANG;

    申请日2007-02-02

  • 分类号H01L21/336;

  • 国家 US

  • 入库时间 2022-08-21 19:29:36

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