Gallium Arsenide Pilot Line for High Performance Components. SARGIC HFET (Self Aligned Refractory Gate Integrated Circuit/Hetro-junction FET) Design Manual

摘要

This manual describes the layout of Gallium Arsenide integrated circuits using SARGIC/HFET (Self Aligned Refractory GAte Integrated Circuit/Hetro-junction FET) process. It is divided into three sections, layout design rules, device terminal characteristics, and process control monitor (PCM). The first section outlines the layout of digital Gallium arsenide circuits in the SARGIC/HFET, 2 micrometers design rules. It describes the circuit layout procedure level by level, and includes the process's layout design rules. The second section contains the terminal characteristics of Enhancement (EHFET), Depletion (DHFET), and diode devices. This includes drain and gate I/V and capacitance curves modeled by AT&T's ADVICE circuit simulator at 25 and 125 C. The last section includes the design and layout of the Process Control Monitor (PCM). The PCM contains test structures for process control and the extraction of circuit simulator models and device S parameters. This allows the foundry to test for process biases, extract process/device parameters, ADVICE models, and gate propagation delays and noise margins. Gallium arsenides (MJM)