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Reconfigurable integrated circuits with scalable architecture including one or more adders

机译:具有可扩展架构的可重构集成电路,包括一个或多个加法器

摘要

An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, an adder, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.
机译:集成电路(IC)包括多个功能块(FB),其中至少一个是可重新配置的。每个FB可以是可重新配置的功能,也可以是不可重新配置的功能,也可以使用其他“嵌套”功能块进行递归扩展。该IC还包括多个输入引脚,多个输出引脚,加法器和多个交叉开关器件。至少在IC级别的元件以这样的方式耦合:所有输入信号都通过交叉开关设备的第一子集提供给FB,所有内部信号通过一个第二子集从一个FB路由到另一个FB。交叉开关设备,并且所有输出信号通过交叉开关设备的第三子集从FB路由到输出引脚。为了提高可路由性和速度,每个交叉开关设备输出均具有单个扇出。另外,每个交叉开关设备可以仅向彼此的交叉开关设备提供一个输入。

著录项

  • 公开/公告号US7498840B2

    专利类型

  • 公开/公告日2009-03-03

    原文格式PDF

  • 申请/专利权人 OLIVIER V. LEPAPE;

    申请/专利号US20070840848

  • 发明设计人 OLIVIER V. LEPAPE;

    申请日2007-08-17

  • 分类号H03K19/177;

  • 国家 US

  • 入库时间 2022-08-21 19:29:20

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