首页> 外国专利> LOW K DIELECTRIC CVD FILM FORMATION PROCESS WITH IN-SITU IMBEDDED NANOLAYERS TO IMPROVE MECHANICAL PROPERTIES

LOW K DIELECTRIC CVD FILM FORMATION PROCESS WITH IN-SITU IMBEDDED NANOLAYERS TO IMPROVE MECHANICAL PROPERTIES

机译:具有原位嵌入纳米层的低K介电CVD膜形成工艺,可改善机械性能

摘要

A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.
机译:具有约3.0或更小的有效介电常数k的低k介电堆叠,其中通过将至少一个纳米层引入介电堆叠来改善堆叠的机械性能。无需显着增加叠层内薄膜的介电常数,也无需对本发明的介电叠层进行任何后处理步骤,即可实现机械性能的改善。具体地,本发明提供了一种低k电介质堆叠,其包括至少一种低k电介质材料和存在于至少一种低k电介质材料中的至少一个纳米层。

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