The error test evasion type test input formation method in 2 pattern tests of the semiconductor integrated circuit

摘要

Being formation method of the test input which impresses test input in the semiconductor integrated circuit and 10 by comparison with the expectation of response decides the breakdown of combinational circuit 17, way the critical path 19 which is formed to the 1st process which decides the test pattern which includes logical value and the undecided value whose decision of breakdown presence is possible and the occasion where test pattern is impressed, 2nd process and the critical path 19 which select 19a and 19b, the critical gate of 19a and 19b the number of state changes which show the 3rd process and the quantity specifies of the critical gate which where gate state changes decreases, undecided valueIt possesses with the 4th process which it decides, critical path 19, it prevents the output delay from 19a and 19b by the fact that the number of state changes is decreased and evades the error test.