TESTING CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT, TESTING METHOD, TESTING PATTERN CREATION METHOD, AND TESTING PATTERN CREATION PROGRAM

摘要

PROBLEM TO BE SOLVED: To enable a testing circuit of a semiconductor integrated circuit using a plurality of clock domains for optionally set the timing-applying double clocks.;SOLUTION: The testing circuit is provided with a double clock extraction circuit for outputting an enable signal, when extraction trigger of the double clocks in a selection trigger clock corresponding to a selection clock out of the plurality of the clock domains of a tested circuit out of a plurality of trigger clocks is detected; a clock-mask circuit for extracting the double clocks from the selection clock, regarding the enable signal as a trigger; and a scan flip-flop for executing a scan testing for the tested circuit by inputting the double clocks. The double clock extraction circuit, the clock mask circuit, and the scan flip-flop are provided, corresponding to the plurality of the clock domains. The extraction trigger is set in each of the selection trigger clocks, on the basis of timing relation that ought to output the double clocks between the plurality of the clock domains.;COPYRIGHT: (C)2012,JPO&INPIT