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APPARATUS AND METHOD FOR IMPLEMENTING HARDWARE SUPPORT FOR DENORMALIZED OPERANDS FOR FLOATING-POINT DIVIDE OPERATIONS
APPARATUS AND METHOD FOR IMPLEMENTING HARDWARE SUPPORT FOR DENORMALIZED OPERANDS FOR FLOATING-POINT DIVIDE OPERATIONS
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机译:用于实现浮点除法操作的非标准化操作的硬件支持的装置和方法
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摘要
A floating-point circuit may include a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor, as well as a divide engine coupled to the normalization circuit. In response to determining that one or more of the input floating-point operands is a denormal number, the operand normalization circuit may be further configured to normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine, and dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ). The divide engine may be configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit.
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