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ARCHITECTURE AND METHOD FOR COMPENSATING FOR DISPARATE SIGNAL RISE AND FALL TIMES BY USING POLARITY SELECTION TO IMPROVE TIMING AND POWER IN AN INTEGRATED CIRCUIT
ARCHITECTURE AND METHOD FOR COMPENSATING FOR DISPARATE SIGNAL RISE AND FALL TIMES BY USING POLARITY SELECTION TO IMPROVE TIMING AND POWER IN AN INTEGRATED CIRCUIT
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机译:通过极性选择来改善集成电路中的时序和功率的,用于补偿离散信号上升和下降时间的体系结构和方法
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摘要
A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing polarities on the longest path to reduce delays; updating the timing graph by transferring new polarity and delay values; performing timing analysis to determine a new longest path if the new longest path is shorter than the prior longest path, accepting a resulting polarity selection and computing minimum delay tuples for the longest path; if the new longest path is not shorter than the prior longest path, accepting a resulting polarity selection and implementing changes in a user-program bitstream.
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