首页> 外国专利> FinFET pMOS double gate semiconductor device with uniaxial tensile strain applied to channel by shrinkable gate electrode material, current flow in 110 crystal orientation, and source and drain Schottky contacts with channel and manufacturing method thereof

FinFET pMOS double gate semiconductor device with uniaxial tensile strain applied to channel by shrinkable gate electrode material, current flow in 110 crystal orientation, and source and drain Schottky contacts with channel and manufacturing method thereof

机译:FinFET pMOS双栅半导体器件,具有通过可收缩的栅电极材料施加到沟道的单轴拉伸应变,<110>晶体取向的电流以及具有沟道的源极和漏极肖特基接触及其制造方法

摘要

A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first 110 crystal orientation, and channels are located at sidewall of the semiconductor layer, a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first 110 crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first 110 crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second 110 crystal orientation perpendicular to the current flow direction, and a gate insulating film that is disposed between the semiconductor layer and the gate electrode, wherein a uniaxial tensile strain is applied to the semiconductor layer in the direction of the second 110 crystal orientation perpendicular to the current flow direction.
机译:具有pMOS双栅结构的半导体器件具有衬底,该衬底的顶表面的晶体取向为(100),由硅或锗制成的半导体层形成在衬底上,使得电流流入第一<110>晶体取向的方向,并且沟道位于半导体层的侧壁,在第一<110>晶体取向的方向上与半导体层的一端相邻的衬底上形成的源极层,以及由金属或金属硅化物制成以与半导体层形成肖特基结。漏极层,其在第一<110>晶体取向的方向上与半导体层的另一端相邻地形成在基板上,并且由金属或金属硅化物制成,以与半导体层形成肖特基结;在垂直于电流流动方向的第二<110>晶体取向的方向上形成在半导体层上的栅电极,以及设置在半导体层和栅电极之间的栅绝缘膜,其中单轴拉伸应变在垂直于电流流动方向的第二<110>晶体取向的方向上将SiO 2施加到半导体层。

著录项

  • 公开/公告号US7755104B2

    专利类型

  • 公开/公告日2010-07-13

    原文格式PDF

  • 申请/专利权人 ATSUSHI YAGISHITA;

    申请/专利号US20070790389

  • 发明设计人 ATSUSHI YAGISHITA;

    申请日2007-04-25

  • 分类号H01L29/04;H01L21/84;

  • 国家 US

  • 入库时间 2022-08-21 18:52:16

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