(110) channel, SiON gate-dielectric PMOS with record high I{sub}(on)=1 mA/μm through channel stress and source drain external resistance (R{sub}(ext)) engineering

摘要

The interest in (110) Si-based devices has been rising in recent years not only because of their 2× hole mobility advantage over conventional (100) PMOS [1], but also because of the ever-increasing importance of (110) channels in advanced FET structures such as FinFETs [2,3] and Tri-gate FETs [4,5]. However, it has been reported that (110) PMOS will face two critical issues which may limit its ultimate performance. First, it has been theoretically predicted that the (110) hole mobility advantage disappears when the channel is stressed beyond 1.2GPa [6], thus projecting a gloomy future for (110) p-type FETs. Second, (110) PMOS has been reported to suffer from higher source/drain external resistance (R{sub}(ext)) than conventional (100) PMOS, which also limits drive current [7]. Although evidence has been published suggesting that (110) PMOS maintains its ～2× mobility advantage over (100) PMOS when combined with both compressive liner and eSiGe stressors, the relatively low drive current reported, due to the severe R{sub}(ext) penalty, could not convincingly reverse the negative impression of (110) channel devices [6,7]. This paper presents for the first time (110) PMOS characteristics without R{sub}(ext) degradation, allowing investigation of fundamental mobility and demonstration of drive current (I{sub}(on)) in excess of 1mA/μm at I{sub}(off)=100nA/μm.