首页> 外国专利> Semiconductor chip scale package incorporating through-vias electrically connected to a substrate and other vias that are isolated from the substrate, and method of forming the package

Semiconductor chip scale package incorporating through-vias electrically connected to a substrate and other vias that are isolated from the substrate, and method of forming the package

机译:半导体芯片级封装,其包括电连接至基板的通孔和与基板隔离的其他通孔,以及形成封装的方法

摘要

A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.
机译:具有通孔的半导体芯片规模封装,其可以被隔离或电连接至基板,以及具有通孔的半导体芯片规模封装的制造方法,其可以被隔离或电连接至基板。

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