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Method and apparatus for designing semiconductor integrated device using noise current and impedance characteristics of input/output buffers between power supply lines

机译:利用电源线之间的输入/输出缓冲器的噪声电流和阻抗特性设计半导体集成器件的方法和装置

摘要

In a method for designing a semiconductor integrated device, there are prepared a first power supply cell having a first decoupling capacitance and a second power supply cell having a second decoupling capacitance larger than the first decoupling capacitance. One of the first and second power supply cells is arranged in each of power supply cell areas of an input/output circuit area of the semiconductor integrated device in accordance with frequency-to-impedance characteristics at a predetermined point of input/output buffers of the input/output circuit area between first and second power supply lines thereof and frequency-to-noise current characteristics of the input/output buffers of the input/output circuit area between the first and second power supply lines.
机译:在用于设计半导体集成器件的方法中,准备具有第一去耦电容的第一电源单元和具有比第一去耦电容大的第二去耦电容的第二电源单元。第一和第二电源单元中的一个根据频率-阻抗特性在半导体集成器件的输入/输出电路区域的每个电源单元区域中布置在半导体集成装置的输入/输出缓冲器的预定点处。第一和第二电源线之间的输入/输出电路区域以及第一和第二电源线之间的输入/输出电路区域的输入/输出缓冲器的频率噪声电流特性。

著录项

  • 公开/公告号US7698670B2

    专利类型

  • 公开/公告日2010-04-13

    原文格式PDF

  • 申请/专利权人 YOSHIHIRO MASUMURA;

    申请/专利号US20070896833

  • 发明设计人 YOSHIHIRO MASUMURA;

    申请日2007-09-06

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 18:50:13

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