A Novel Low Input Impedance Low Power Fully Differential Current Buffer with ±0.65V Supply Voltage and high bandwidth of 520MHz

摘要

A new fully differential (FD) low input impedance CMOS current buffer with low voltage, and low power operation is presented. The low input impedance is achieved by remarkable reduction of the input node voltage swing using a novel double feedback scheme. Some advantages of the proposed double feedback scheme over the conventional (either positive or negative) feedback techniques are: lower input impedance, robustness to process tolerances and a very simple and compact design. As a fundamental building block, this current buffer can also be used to implement such current mode circuits as current conveyors, current differencing buffered amplifiers (CDBA), current mode operational amplifiers, oscillators, filters and some voltage operational amplifiers (VOA). The proposed current buffer is designed and simulated with HSPICE using TSMC 0.18μm CMOS process parameters and supply voltage of ±0.65V. The simulated input impedance is 0.44Ω which shows a reduction factor of 6250 compared to the conventional common gate structure. It exhibits excellent -3dB bandwidth of 520MHz and low power consumption of 180μW which stem from its very simple structure. The proposed current buffer also exhibits high common mode rejection ratio (CMRR) of 90dB, very high positive and negative power supply rejection ratio (PSRR+/PSRR-) of 112dB and 143dB respectively which makes it very suitable for low voltage mixed mode applications. The corner case and Monte Carlo simulation results are also provided which proves the outstanding robust performance of the proposed current buffer against technology process tolerances.