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System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation

机译:在不同的时序方案中使用测试模式重新执行以进行处理器设计验证和确认的测试系统和方法

摘要

A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor's memory (cache, TLB, SLB, etc.) that, in turn, varies the timing scenarios when re-executing test patterns. By re-executing the test patterns instead of rebuilding new test patterns, verification quality is improved since more time is available for execution, verification and validation. In addition, since the test patterns result in the same final state, the invention described herein also simplifies error checking.
机译:提出了一种使用测试模式重新执行的系统和方法处理器测试。处理器使用不同的时序方案重新执行测试模式,以减少测试模式的构建时间并增加系统测试范围。本文描述的发明改变了处理器的存储器(高速缓存,TLB,SLB等)的初始状态,继而改变了重新执行测试模式时的时序方案。通过重新执行测试模式而不是重新构建新的测试模式,可以提高验证质量,因为有更多时间可以执行,验证和确认。另外,由于测试图案导致相同的最终状态,因此本文所述的发明还简化了错误检查。

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