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Caching technique for electrical simulation of VLSI interconnect
Caching technique for electrical simulation of VLSI interconnect
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机译:VLSI互连的电气仿真缓存技术
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摘要
Circuits, methods, and apparatus for including interconnect parasitics without greatly increasing circuit simulation complexity and run times. Interconnect paths are reduced to one of a number of simplified topologies based on path width, length, or other parameters. The input drive waveform is similarly approximated. A grid array is formed in advance, where each point in the grid array corresponds to a set of values relating to a path topology, input waveform, and resulting output waveform. The simplified interconnect path and input waveform are mapped into a set of parameters which corresponds to a location in the predetermined grid array. The output waveform is determined by interpolating output waveforms from gridpoints surrounding the location.
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